// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  peri_cfg_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  Huawei
// Version       :  1.0
// Date          :  2017/11/13
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/03/16 18:04:33 Create file
// ******************************************************************************

#ifndef __PERI_CFG_REG_OFFSET_FIELD_H__
#define __PERI_CFG_REG_OFFSET_FIELD_H__

#define PERI_CFG_ICG_EN_ITS_LEN    1
#define PERI_CFG_ICG_EN_ITS_OFFSET 0

#define PERI_CFG_ICG_DIS_ITS_LEN    1
#define PERI_CFG_ICG_DIS_ITS_OFFSET 0

#define PERI_CFG_ICG_EN_FTE_LEN    1
#define PERI_CFG_ICG_EN_FTE_OFFSET 0

#define PERI_CFG_ICG_DIS_FTE_LEN    1
#define PERI_CFG_ICG_DIS_FTE_OFFSET 0

#define PERI_CFG_ICG_EN_DBG_LEN    1
#define PERI_CFG_ICG_EN_DBG_OFFSET 0

#define PERI_CFG_ICG_DIS_DBG_LEN    1
#define PERI_CFG_ICG_DIS_DBG_OFFSET 0

#define PERI_CFG_ICG_EN_M3_LEN    1
#define PERI_CFG_ICG_EN_M3_OFFSET 0

#define PERI_CFG_ICG_DIS_M3_LEN    1
#define PERI_CFG_ICG_DIS_M3_OFFSET 0

#define PERI_CFG_ICG_EN_GPIO_LEN    2
#define PERI_CFG_ICG_EN_GPIO_OFFSET 0

#define PERI_CFG_ICG_DIS_GPIO_LEN    2
#define PERI_CFG_ICG_DIS_GPIO_OFFSET 0

#define PERI_CFG_ICG_EN_GIC_LEN    1
#define PERI_CFG_ICG_EN_GIC_OFFSET 0

#define PERI_CFG_ICG_DIS_GIC_LEN    1
#define PERI_CFG_ICG_DIS_GIC_OFFSET 0

#define PERI_CFG_ICG_EN_SMMU_TRANS_LEN    1
#define PERI_CFG_ICG_EN_SMMU_TRANS_OFFSET 0

#define PERI_CFG_ICG_DIS_SMMU_TRANS_LEN    1
#define PERI_CFG_ICG_DIS_SMMU_TRANS_OFFSET 0

#define PERI_CFG_ICG_EN_TIMER0_LEN    30
#define PERI_CFG_ICG_EN_TIMER0_OFFSET 0

#define PERI_CFG_ICG_DIS_TIMER0_LEN    30
#define PERI_CFG_ICG_DIS_TIMER0_OFFSET 0

#define PERI_CFG_ICG_EN_TIMER1_LEN    32
#define PERI_CFG_ICG_EN_TIMER1_OFFSET 0

#define PERI_CFG_ICG_DIS_TIMER1_LEN    32
#define PERI_CFG_ICG_DIS_TIMER1_OFFSET 0

#define PERI_CFG_ICG_EN_TIMER2_LEN    32
#define PERI_CFG_ICG_EN_TIMER2_OFFSET 0

#define PERI_CFG_ICG_DIS_TIMER2_LEN    32
#define PERI_CFG_ICG_DIS_TIMER2_OFFSET 0

#define PERI_CFG_ICG_EN_WDOG_LEN    11
#define PERI_CFG_ICG_EN_WDOG_OFFSET 0

#define PERI_CFG_ICG_DIS_WDOG_LEN    11
#define PERI_CFG_ICG_DIS_WDOG_OFFSET 0

#define PERI_CFG_ICG_EN_UART_LEN    1
#define PERI_CFG_ICG_EN_UART_OFFSET 0

#define PERI_CFG_ICG_DIS_UART_LEN    1
#define PERI_CFG_ICG_DIS_UART_OFFSET 0

#define PERI_CFG_ICG_EN_MDIO_LEN    2
#define PERI_CFG_ICG_EN_MDIO_OFFSET 0

#define PERI_CFG_ICG_DIS_MDIO_LEN    2
#define PERI_CFG_ICG_DIS_MDIO_OFFSET 0

#define PERI_CFG_ICG_EN_SMB_LEN    1
#define PERI_CFG_ICG_EN_SMB_OFFSET 0

#define PERI_CFG_ICG_DIS_SMB_LEN    1
#define PERI_CFG_ICG_DIS_SMB_OFFSET 0

#define PERI_CFG_ICG_EN_CER_S_LEN    1
#define PERI_CFG_ICG_EN_CER_S_OFFSET 1
#define PERI_CFG_ICG_EN_CER_M_LEN    1
#define PERI_CFG_ICG_EN_CER_M_OFFSET 0

#define PERI_CFG_ICG_DIS_CER_S_LEN    1
#define PERI_CFG_ICG_DIS_CER_S_OFFSET 1
#define PERI_CFG_ICG_DIS_CER_M_LEN    1
#define PERI_CFG_ICG_DIS_CER_M_OFFSET 0

#define PERI_CFG_ICG_EN_SFC2X_LEN    1
#define PERI_CFG_ICG_EN_SFC2X_OFFSET 0

#define PERI_CFG_ICG_DIS_SFC2X_LEN    1
#define PERI_CFG_ICG_DIS_SFC2X_OFFSET 0

#define PERI_CFG_ICG_EN_SFC1X_LEN    1
#define PERI_CFG_ICG_EN_SFC1X_OFFSET 0

#define PERI_CFG_ICG_DIS_SFC1X_LEN    1
#define PERI_CFG_ICG_DIS_SFC1X_OFFSET 0

#define PERI_CFG_ICG_EN_SDMA_LEN    1
#define PERI_CFG_ICG_EN_SDMA_OFFSET 0

#define PERI_CFG_ICG_DIS_SDMA_LEN    1
#define PERI_CFG_ICG_DIS_SDMA_OFFSET 0

#define PERI_CFG_ICG_EN_TRNG_LEN    1
#define PERI_CFG_ICG_EN_TRNG_OFFSET 0

#define PERI_CFG_ICG_DIS_TRNG_LEN    1
#define PERI_CFG_ICG_DIS_TRNG_OFFSET 0

#define PERI_CFG_ICG_EN_EMMC_LEN    1
#define PERI_CFG_ICG_EN_EMMC_OFFSET 0

#define PERI_CFG_ICG_DIS_EMMC_LEN    1
#define PERI_CFG_ICG_DIS_EMMC_OFFSET 0

#define PERI_CFG_SRST_REQ_ITS_LEN    1
#define PERI_CFG_SRST_REQ_ITS_OFFSET 0

#define PERI_CFG_SRST_DREQ_ITS_LEN    1
#define PERI_CFG_SRST_DREQ_ITS_OFFSET 0

#define PERI_CFG_SRST_REQ_FTE_LEN    1
#define PERI_CFG_SRST_REQ_FTE_OFFSET 0

#define PERI_CFG_SRST_DREQ_FTE_LEN    1
#define PERI_CFG_SRST_DREQ_FTE_OFFSET 0

#define PERI_CFG_SRST_REQ_DBG_LEN    1
#define PERI_CFG_SRST_REQ_DBG_OFFSET 0

#define PERI_CFG_SRST_DREQ_DBG_LEN    1
#define PERI_CFG_SRST_DREQ_DBG_OFFSET 0

#define PERI_CFG_SRST_REQ_GPIO_LEN    2
#define PERI_CFG_SRST_REQ_GPIO_OFFSET 0

#define PERI_CFG_SRST_DREQ_GPIO_LEN    2
#define PERI_CFG_SRST_DREQ_GPIO_OFFSET 0

#define PERI_CFG_SRST_REQ_WDOG_LEN    11
#define PERI_CFG_SRST_REQ_WDOG_OFFSET 0

#define PERI_CFG_SRST_DREQ_WDOG_LEN    11
#define PERI_CFG_SRST_DREQ_WDOG_OFFSET 0

#define PERI_CFG_SRST_REQ_GIC_LEN    1
#define PERI_CFG_SRST_REQ_GIC_OFFSET 0

#define PERI_CFG_SRST_DREQ_GIC_LEN    1
#define PERI_CFG_SRST_DREQ_GIC_OFFSET 0

#define PERI_CFG_SRST_REQ_UART_LEN    1
#define PERI_CFG_SRST_REQ_UART_OFFSET 0

#define PERI_CFG_SRST_DREQ_UART_LEN    1
#define PERI_CFG_SRST_DREQ_UART_OFFSET 0

#define PERI_CFG_SRST_REQ_MDIO_LEN    2
#define PERI_CFG_SRST_REQ_MDIO_OFFSET 0

#define PERI_CFG_SRST_DREQ_MDIO_LEN    2
#define PERI_CFG_SRST_DREQ_MDIO_OFFSET 0

#define PERI_CFG_SRST_REQ_M3_7_LEN       1
#define PERI_CFG_SRST_REQ_M3_7_OFFSET    15
#define PERI_CFG_SRST_REQ_M3_6_LEN       1
#define PERI_CFG_SRST_REQ_M3_6_OFFSET    14
#define PERI_CFG_SRST_REQ_M3_5_LEN       1
#define PERI_CFG_SRST_REQ_M3_5_OFFSET    13
#define PERI_CFG_SRST_REQ_M3_4_LEN       1
#define PERI_CFG_SRST_REQ_M3_4_OFFSET    12
#define PERI_CFG_SRST_REQ_M3_3_LEN       1
#define PERI_CFG_SRST_REQ_M3_3_OFFSET    11
#define PERI_CFG_SRST_REQ_M3_2_LEN       1
#define PERI_CFG_SRST_REQ_M3_2_OFFSET    10
#define PERI_CFG_SRST_REQ_M3_1_LEN       1
#define PERI_CFG_SRST_REQ_M3_1_OFFSET    9
#define PERI_CFG_SRST_REQ_M3_0_LEN       1
#define PERI_CFG_SRST_REQ_M3_0_OFFSET    8
#define PERI_CFG_SRST_REQ_M3_POR7_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR7_OFFSET 7
#define PERI_CFG_SRST_REQ_M3_POR6_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR6_OFFSET 6
#define PERI_CFG_SRST_REQ_M3_POR5_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR5_OFFSET 5
#define PERI_CFG_SRST_REQ_M3_POR4_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR4_OFFSET 4
#define PERI_CFG_SRST_REQ_M3_POR3_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR3_OFFSET 3
#define PERI_CFG_SRST_REQ_M3_POR2_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR2_OFFSET 2
#define PERI_CFG_SRST_REQ_M3_POR1_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR1_OFFSET 1
#define PERI_CFG_SRST_REQ_M3_POR0_LEN    1
#define PERI_CFG_SRST_REQ_M3_POR0_OFFSET 0

#define PERI_CFG_SRST_DREQ_M3_7_LEN       1
#define PERI_CFG_SRST_DREQ_M3_7_OFFSET    15
#define PERI_CFG_SRST_DREQ_M3_6_LEN       1
#define PERI_CFG_SRST_DREQ_M3_6_OFFSET    14
#define PERI_CFG_SRST_DREQ_M3_5_LEN       1
#define PERI_CFG_SRST_DREQ_M3_5_OFFSET    13
#define PERI_CFG_SRST_DREQ_M3_4_LEN       1
#define PERI_CFG_SRST_DREQ_M3_4_OFFSET    12
#define PERI_CFG_SRST_DREQ_M3_3_LEN       1
#define PERI_CFG_SRST_DREQ_M3_3_OFFSET    11
#define PERI_CFG_SRST_DREQ_M3_2_LEN       1
#define PERI_CFG_SRST_DREQ_M3_2_OFFSET    10
#define PERI_CFG_SRST_DREQ_M3_1_LEN       1
#define PERI_CFG_SRST_DREQ_M3_1_OFFSET    9
#define PERI_CFG_SRST_DREQ_M3_0_LEN       1
#define PERI_CFG_SRST_DREQ_M3_0_OFFSET    8
#define PERI_CFG_SRST_DREQ_M3_POR7_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR7_OFFSET 7
#define PERI_CFG_SRST_DREQ_M3_POR6_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR6_OFFSET 6
#define PERI_CFG_SRST_DREQ_M3_POR5_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR5_OFFSET 5
#define PERI_CFG_SRST_DREQ_M3_POR4_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR4_OFFSET 4
#define PERI_CFG_SRST_DREQ_M3_POR3_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR3_OFFSET 3
#define PERI_CFG_SRST_DREQ_M3_POR2_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR2_OFFSET 2
#define PERI_CFG_SRST_DREQ_M3_POR1_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR1_OFFSET 1
#define PERI_CFG_SRST_DREQ_M3_POR0_LEN    1
#define PERI_CFG_SRST_DREQ_M3_POR0_OFFSET 0

#define PERI_CFG_SRST_REQ_SMB_LEN    1
#define PERI_CFG_SRST_REQ_SMB_OFFSET 0

#define PERI_CFG_SRST_DREQ_SMB_LEN    1
#define PERI_CFG_SRST_DREQ_SMB_OFFSET 0

#define PERI_CFG_SRST_REQ_CER_S_LEN    1
#define PERI_CFG_SRST_REQ_CER_S_OFFSET 1
#define PERI_CFG_SRST_REQ_CER_M_LEN    1
#define PERI_CFG_SRST_REQ_CER_M_OFFSET 0

#define PERI_CFG_SRST_DREQ_CER_S_LEN    1
#define PERI_CFG_SRST_DREQ_CER_S_OFFSET 1
#define PERI_CFG_SRST_DREQ_CER_M_LEN    1
#define PERI_CFG_SRST_DREQ_CER_M_OFFSET 0

#define PERI_CFG_SRST_REQ_TIMER_LEN    30
#define PERI_CFG_SRST_REQ_TIMER_OFFSET 0

#define PERI_CFG_SRST_DREQ_TIMER_LEN    30
#define PERI_CFG_SRST_DREQ_TIMER_OFFSET 0

#define PERI_CFG_SRST_REQ_SFC_BUS_LEN    1
#define PERI_CFG_SRST_REQ_SFC_BUS_OFFSET 2
#define PERI_CFG_SRST_REQ_SFC2X_LEN      1
#define PERI_CFG_SRST_REQ_SFC2X_OFFSET   1
#define PERI_CFG_SRST_REQ_SFC1X_LEN      1
#define PERI_CFG_SRST_REQ_SFC1X_OFFSET   0

#define PERI_CFG_SRST_DREQ_SFC_BUS_LEN    1
#define PERI_CFG_SRST_DREQ_SFC_BUS_OFFSET 2
#define PERI_CFG_SRST_DREQ_SFC2X_LEN      1
#define PERI_CFG_SRST_DREQ_SFC2X_OFFSET   1
#define PERI_CFG_SRST_DREQ_SFC1X_LEN      1
#define PERI_CFG_SRST_DREQ_SFC1X_OFFSET   0

#define PERI_CFG_SRST_REQ_SDMA_LEN    1
#define PERI_CFG_SRST_REQ_SDMA_OFFSET 0

#define PERI_CFG_SRST_DREQ_SDMA_LEN    1
#define PERI_CFG_SRST_DREQ_SDMA_OFFSET 0

#define PERI_CFG_SRST_REQ_TRNG_LEN    1
#define PERI_CFG_SRST_REQ_TRNG_OFFSET 0

#define PERI_CFG_SRST_DREQ_TRNG_LEN    1
#define PERI_CFG_SRST_DREQ_TRNG_OFFSET 0

#define PERI_CFG_SRST_REQ_EMMC_LEN    1
#define PERI_CFG_SRST_REQ_EMMC_OFFSET 0

#define PERI_CFG_SRST_DREQ_EMMC_LEN    1
#define PERI_CFG_SRST_DREQ_EMMC_OFFSET 0

#define PERI_CFG_CHAIN_ERR_INT_LEN    1
#define PERI_CFG_CHAIN_ERR_INT_OFFSET 0

#define PERI_CFG_CHAIN_ERR_INTMASK_LEN    1
#define PERI_CFG_CHAIN_ERR_INTMASK_OFFSET 0

#define PERI_CFG_CHAIN_ERR_INTSTATUS_LEN    1
#define PERI_CFG_CHAIN_ERR_INTSTATUS_OFFSET 0

#define PERI_CFG_CHAIN_ERR_CPU_INT_LEN    1
#define PERI_CFG_CHAIN_ERR_CPU_INT_OFFSET 0

#define PERI_CFG_CHAIN_ERR_CPU_INTMASK_LEN    1
#define PERI_CFG_CHAIN_ERR_CPU_INTMASK_OFFSET 0

#define PERI_CFG_CHAIN_ERR_CPU_INTSTATUS_LEN    1
#define PERI_CFG_CHAIN_ERR_CPU_INTSTATUS_OFFSET 0

#define PERI_CFG_ERRRSP_DISABLE_LEN    1
#define PERI_CFG_ERRRSP_DISABLE_OFFSET 0

#define PERI_CFG_M3_DBGEN_LEN      1
#define PERI_CFG_M3_DBGEN_OFFSET   30
#define PERI_CFG_M3_RXEV_LEN       1
#define PERI_CFG_M3_RXEV_OFFSET    27
#define PERI_CFG_M3_INTNMI_LEN     1
#define PERI_CFG_M3_INTNMI_OFFSET  26
#define PERI_CFG_M3_STCALIB_LEN    26
#define PERI_CFG_M3_STCALIB_OFFSET 0

#define PERI_CFG_M3_NIDEN_LEN           1
#define PERI_CFG_M3_NIDEN_OFFSET        25
#define PERI_CFG_M3_DAPEN_LEN           1
#define PERI_CFG_M3_DAPEN_OFFSET        24
#define PERI_CFG_M3_BOOTROM_ADDR_LEN    24
#define PERI_CFG_M3_BOOTROM_ADDR_OFFSET 0

#define PERI_CFG_TSENSOR1_ULTRA_HIGH_LEN    10
#define PERI_CFG_TSENSOR1_ULTRA_HIGH_OFFSET 20
#define PERI_CFG_TSENSOR1_HIGH_LEN          10
#define PERI_CFG_TSENSOR1_HIGH_OFFSET       10
#define PERI_CFG_TSENSOR1_LOW_LEN           10
#define PERI_CFG_TSENSOR1_LOW_OFFSET        0

#define PERI_CFG_TSENSOR1_SAMPLE_SHIFT_NUM_LEN    4
#define PERI_CFG_TSENSOR1_SAMPLE_SHIFT_NUM_OFFSET 0

#define PERI_CFG_TSENSOR1_TEMP_CT_SEL_LEN    2
#define PERI_CFG_TSENSOR1_TEMP_CT_SEL_OFFSET 12
#define PERI_CFG_TSENSOR1_TEMP_CALIB_LEN     1
#define PERI_CFG_TSENSOR1_TEMP_CALIB_OFFSET  1
#define PERI_CFG_TSENSOR1_TEMP_EN_LEN        1
#define PERI_CFG_TSENSOR1_TEMP_EN_OFFSET     0

#define PERI_CFG_AXI_USER_ULTRASOC_LEN    6
#define PERI_CFG_AXI_USER_ULTRASOC_OFFSET 0

#define PERI_CFG_ULTRASOC_MSG_SEL_LEN    1
#define PERI_CFG_ULTRASOC_MSG_SEL_OFFSET 0

#define PERI_CFG_AXI_USER_NS_ULTRASOC_LEN    1
#define PERI_CFG_AXI_USER_NS_ULTRASOC_OFFSET 0

#define PERI_CFG_WTSEL_ETF_LEN         2
#define PERI_CFG_WTSEL_ETF_OFFSET      4
#define PERI_CFG_RTSEL_ETF_LEN         2
#define PERI_CFG_RTSEL_ETF_OFFSET      2
#define PERI_CFG_ULTRASOC_NIDEN_LEN    1
#define PERI_CFG_ULTRASOC_NIDEN_OFFSET 1
#define PERI_CFG_ULTRASOC_DBGEN_LEN    1
#define PERI_CFG_ULTRASOC_DBGEN_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_EN_LEN    16
#define PERI_CFG_M3_REMAP_ADDR_EN_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_0_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_0_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_1_LEN    16
#define PERI_CFG_M3_REMAP_ADDR_1_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_2_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_2_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_3_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_3_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_4_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_4_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_5_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_5_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_6_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_6_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_7_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_7_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_8_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_8_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_9_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_9_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_10_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_10_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_11_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_11_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_12_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_12_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_13_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_13_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_14_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_14_OFFSET 0

#define PERI_CFG_M3_REMAP_ADDR_15_LEN    12
#define PERI_CFG_M3_REMAP_ADDR_15_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_L_M3_0_LEN    32
#define PERI_CFG_SC_CFG_AXUSER_L_M3_0_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_M_M3_0_LEN    32
#define PERI_CFG_SC_CFG_AXUSER_M_M3_0_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_H_M3_0_LEN    4
#define PERI_CFG_SC_CFG_AXUSER_H_M3_0_OFFSET 0

#define PERI_CFG_SC_CFG_AXCACHE_M3_0_LEN    4
#define PERI_CFG_SC_CFG_AXCACHE_M3_0_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_L_M3_1_LEN    32
#define PERI_CFG_SC_CFG_AXUSER_L_M3_1_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_M_M3_1_LEN    32
#define PERI_CFG_SC_CFG_AXUSER_M_M3_1_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_H_M3_1_LEN    4
#define PERI_CFG_SC_CFG_AXUSER_H_M3_1_OFFSET 0

#define PERI_CFG_SC_CFG_AXCACHE_M3_1_LEN    4
#define PERI_CFG_SC_CFG_AXCACHE_M3_1_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_L_M3_2_LEN    32
#define PERI_CFG_SC_CFG_AXUSER_L_M3_2_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_M_M3_2_LEN    32
#define PERI_CFG_SC_CFG_AXUSER_M_M3_2_OFFSET 0

#define PERI_CFG_SC_CFG_AXUSER_H_M3_2_LEN    4
#define PERI_CFG_SC_CFG_AXUSER_H_M3_2_OFFSET 0

#define PERI_CFG_SC_CFG_AXCACHE_M3_2_LEN    4
#define PERI_CFG_SC_CFG_AXCACHE_M3_2_OFFSET 0

#define PERI_CFG_SC_ARQOS_M3_LEN    4
#define PERI_CFG_SC_ARQOS_M3_OFFSET 4
#define PERI_CFG_SC_AWQOS_M3_LEN    4
#define PERI_CFG_SC_AWQOS_M3_OFFSET 0

#define PERI_CFG_SC_ARQOS_GIC_LEN    4
#define PERI_CFG_SC_ARQOS_GIC_OFFSET 4
#define PERI_CFG_SC_AWQOS_GIC_LEN    4
#define PERI_CFG_SC_AWQOS_GIC_OFFSET 0

#define PERI_CFG_SC_ARQOS_EMMC_LEN    4
#define PERI_CFG_SC_ARQOS_EMMC_OFFSET 4
#define PERI_CFG_SC_AWQOS_EMMC_LEN    4
#define PERI_CFG_SC_AWQOS_EMMC_OFFSET 0

#define PERI_CFG_SC_ARQOS_SDMAM_LEN    4
#define PERI_CFG_SC_ARQOS_SDMAM_OFFSET 4
#define PERI_CFG_SC_AWQOS_SDMAM_LEN    4
#define PERI_CFG_SC_AWQOS_SDMAM_OFFSET 0

#define PERI_CFG_SC_M2_PERST_INT_POLARITY_LEN    1
#define PERI_CFG_SC_M2_PERST_INT_POLARITY_OFFSET 13
#define PERI_CFG_SC_GE_PHY_INT_POLARITY_LEN      1
#define PERI_CFG_SC_GE_PHY_INT_POLARITY_OFFSET   12
#define PERI_CFG_SC_GPHY_INT_POLARITY_LEN        1
#define PERI_CFG_SC_GPHY_INT_POLARITY_OFFSET     11
#define PERI_CFG_SC_PMU_INT_POLARITY_LEN         2
#define PERI_CFG_SC_PMU_INT_POLARITY_OFFSET      9
#define PERI_CFG_SC_EXT_INT_POLARITY_LEN         9
#define PERI_CFG_SC_EXT_INT_POLARITY_OFFSET      0

#define PERI_CFG_SC_CMD_DELAY_EN_CFGBUS_LEN    1
#define PERI_CFG_SC_CMD_DELAY_EN_CFGBUS_OFFSET 0

#define PERI_CFG_SC_COUNTER_CMD_DELAY_CFGBUS_LEN    32
#define PERI_CFG_SC_COUNTER_CMD_DELAY_CFGBUS_OFFSET 0

#define PERI_CFG_SC_CMD_DELAY_EN_CFGBUS_DBG_LEN    1
#define PERI_CFG_SC_CMD_DELAY_EN_CFGBUS_DBG_OFFSET 0

#define PERI_CFG_SC_COUNTER_CMD_DELAY_CFGBUS_DBG_LEN    32
#define PERI_CFG_SC_COUNTER_CMD_DELAY_CFGBUS_DBG_OFFSET 0

#define PERI_CFG_MEM_POWER_MODE_SMMU_LEN    6
#define PERI_CFG_MEM_POWER_MODE_SMMU_OFFSET 7
#define PERI_CFG_SP_RAM_TMOD_SMMU_LEN       7
#define PERI_CFG_SP_RAM_TMOD_SMMU_OFFSET    0

#define PERI_CFG_SP_RAM_TMOD_GIC_LEN    7
#define PERI_CFG_SP_RAM_TMOD_GIC_OFFSET 0

#define PERI_CFG_SP_RAM_TMOD_ULTRASOC_LEN    7
#define PERI_CFG_SP_RAM_TMOD_ULTRASOC_OFFSET 0

#define PERI_CFG_MEM_POWER_MODE_CER_LEN    6
#define PERI_CFG_MEM_POWER_MODE_CER_OFFSET 7
#define PERI_CFG_SP_RAM_TMOD_CER_LEN       7
#define PERI_CFG_SP_RAM_TMOD_CER_OFFSET    0

#define PERI_CFG_MEM_POWER_MODE_TRNG_LEN    6
#define PERI_CFG_MEM_POWER_MODE_TRNG_OFFSET 7
#define PERI_CFG_SP_RAM_TMOD_TRNG_LEN       7
#define PERI_CFG_SP_RAM_TMOD_TRNG_OFFSET    0

#define PERI_CFG_TIMER64_EN_EXTERNA_LEN    10
#define PERI_CFG_TIMER64_EN_EXTERNA_OFFSET 0

#define PERI_CFG_CRG_SRST_WDOG_EN_LEN    32
#define PERI_CFG_CRG_SRST_WDOG_EN_OFFSET 0

#define PERI_CFG_TIMER_CLK_SEL_LEN    2
#define PERI_CFG_TIMER_CLK_SEL_OFFSET 0

#define PERI_CFG_SC_BUS_NUM_LEN    8
#define PERI_CFG_SC_BUS_NUM_OFFSET 0

#define PERI_CFG_SC_DEV_NUM_LEN    8
#define PERI_CFG_SC_DEV_NUM_OFFSET 0

#define PERI_CFG_RD_WAIT_CYCLE_LEN        10
#define PERI_CFG_RD_WAIT_CYCLE_OFFSET     10
#define PERI_CFG_RD_WAIT_CYCLE_CPU_LEN    10
#define PERI_CFG_RD_WAIT_CYCLE_CPU_OFFSET 0

#define PERI_CFG_EMMC_CLK_SEL_LEN    1
#define PERI_CFG_EMMC_CLK_SEL_OFFSET 0

#define PERI_CFG_SC_AXI_USER_L32_EMMC_LEN    32
#define PERI_CFG_SC_AXI_USER_L32_EMMC_OFFSET 0

#define PERI_CFG_SC_AXI_USER_H32_EMMC_LEN    32
#define PERI_CFG_SC_AXI_USER_H32_EMMC_OFFSET 0

#define PERI_CFG_SC_AXI_USER_H67_64_EMMC_LEN    4
#define PERI_CFG_SC_AXI_USER_H67_64_EMMC_OFFSET 0

#define PERI_CFG_SC_AXI_CACHE_EMMC_LEN    4
#define PERI_CFG_SC_AXI_CACHE_EMMC_OFFSET 0

#define PERI_CFG_SC_AXI_PORT_SEL_LEN    1
#define PERI_CFG_SC_AXI_PORT_SEL_OFFSET 0

#define PERI_CFG_SC_BYP_EN_SFC_MEM_LEN    1
#define PERI_CFG_SC_BYP_EN_SFC_MEM_OFFSET 1
#define PERI_CFG_SC_BYP_EN_SFC_REG_LEN    1
#define PERI_CFG_SC_BYP_EN_SFC_REG_OFFSET 0

#define PERI_CFG_SC_BYP_EN_SMB_LEN    1
#define PERI_CFG_SC_BYP_EN_SMB_OFFSET 1
#define PERI_CFG_SC_BYP_EN_CER_LEN    1
#define PERI_CFG_SC_BYP_EN_CER_OFFSET 0

#define PERI_CFG_SC_UART_SEL_LEN    3
#define PERI_CFG_SC_UART_SEL_OFFSET 0

#define PERI_CFG_SC_AXQOS_ULTRASOC_LEN      4
#define PERI_CFG_SC_AXQOS_ULTRASOC_OFFSET   4
#define PERI_CFG_SC_AXCACHE_ULTRASOC_LEN    4
#define PERI_CFG_SC_AXCACHE_ULTRASOC_OFFSET 0

#define PERI_CFG_SC_ARPROT_ULTRASOC_LEN    3
#define PERI_CFG_SC_ARPROT_ULTRASOC_OFFSET 3
#define PERI_CFG_SC_AWPROT_ULTRASOC_LEN    3
#define PERI_CFG_SC_AWPROT_ULTRASOC_OFFSET 0

#define PERI_CFG_SC_DAW_EN_LEN      1
#define PERI_CFG_SC_DAW_EN_OFFSET   25
#define PERI_CFG_SC_DAW_SIZE_LEN    5
#define PERI_CFG_SC_DAW_SIZE_OFFSET 20
#define PERI_CFG_SC_DAW_ADDR_LEN    12
#define PERI_CFG_SC_DAW_ADDR_OFFSET 0

#define PERI_CFG_SC_AHB_HADDR_39_EMMC_LEN    1
#define PERI_CFG_SC_AHB_HADDR_39_EMMC_OFFSET 0

#define PERI_CFG_EXT_INT_MASK_LEN    14
#define PERI_CFG_EXT_INT_MASK_OFFSET 0

#define PERI_CFG_HIPCIE_INT_MASK_LEN     1
#define PERI_CFG_HIPCIE_INT_MASK_OFFSET  2
#define PERI_CFG_TIMER64_INT_MASK_LEN    1
#define PERI_CFG_TIMER64_INT_MASK_OFFSET 1
#define PERI_CFG_GPIO0_INT_MASK_LEN      1
#define PERI_CFG_GPIO0_INT_MASK_OFFSET   0

#define PERI_CFG_TSENSOR1_ULTRA_OVER_LEN    1
#define PERI_CFG_TSENSOR1_ULTRA_OVER_OFFSET 2
#define PERI_CFG_TSENSOR1_OVER_LEN          1
#define PERI_CFG_TSENSOR1_OVER_OFFSET       1
#define PERI_CFG_TSENSOR1_UNDER_LEN         1
#define PERI_CFG_TSENSOR1_UNDER_OFFSET      0

#define PERI_CFG_TSENSOR1_ULTRA_OVER_INT_MASK_LEN    1
#define PERI_CFG_TSENSOR1_ULTRA_OVER_INT_MASK_OFFSET 2
#define PERI_CFG_TSENSOR1_OVER_INT_MASK_LEN          1
#define PERI_CFG_TSENSOR1_OVER_INT_MASK_OFFSET       1
#define PERI_CFG_TSENSOR1_UNDER_INT_MASK_LEN         1
#define PERI_CFG_TSENSOR1_UNDER_INT_MASK_OFFSET      0

#define PERI_CFG_PCIE_PERST_LEN    1
#define PERI_CFG_PCIE_PERST_OFFSET 0

#define PERI_CFG_PCIE_PERST_INT_MASK_LEN    1
#define PERI_CFG_PCIE_PERST_INT_MASK_OFFSET 0

#define PERI_CFG_PWR_CORE_LEN    8
#define PERI_CFG_PWR_CORE_OFFSET 0

#define PERI_CFG_PWR_CORE_INT_MASK_LEN    8
#define PERI_CFG_PWR_CORE_INT_MASK_OFFSET 0

#define PERI_CFG_ICG_ST_ITS_LEN    1
#define PERI_CFG_ICG_ST_ITS_OFFSET 0

#define PERI_CFG_ICG_ST_FTE_LEN    1
#define PERI_CFG_ICG_ST_FTE_OFFSET 0

#define PERI_CFG_ICG_ST_DBG_LEN    1
#define PERI_CFG_ICG_ST_DBG_OFFSET 0

#define PERI_CFG_ICG_ST_M3_LEN    1
#define PERI_CFG_ICG_ST_M3_OFFSET 0

#define PERI_CFG_ICG_ST_GPIO_LEN    2
#define PERI_CFG_ICG_ST_GPIO_OFFSET 0

#define PERI_CFG_ICG_ST_GIC_LEN    1
#define PERI_CFG_ICG_ST_GIC_OFFSET 0

#define PERI_CFG_ICG_ST_SMMU_TRANS_LEN    1
#define PERI_CFG_ICG_ST_SMMU_TRANS_OFFSET 0

#define PERI_CFG_ICG_ST_TIMER0_LEN    30
#define PERI_CFG_ICG_ST_TIMER0_OFFSET 0

#define PERI_CFG_ICG_ST_TIMER1_LEN    32
#define PERI_CFG_ICG_ST_TIMER1_OFFSET 0

#define PERI_CFG_ICG_ST_TIMER2_LEN    32
#define PERI_CFG_ICG_ST_TIMER2_OFFSET 0

#define PERI_CFG_ICG_ST_WDOG_LEN    11
#define PERI_CFG_ICG_ST_WDOG_OFFSET 0

#define PERI_CFG_ICG_ST_UART_LEN    1
#define PERI_CFG_ICG_ST_UART_OFFSET 0

#define PERI_CFG_ICG_ST_MDIO_LEN    2
#define PERI_CFG_ICG_ST_MDIO_OFFSET 0

#define PERI_CFG_ICG_ST_SMB_LEN    1
#define PERI_CFG_ICG_ST_SMB_OFFSET 0

#define PERI_CFG_ICG_ST_CER_S_LEN    1
#define PERI_CFG_ICG_ST_CER_S_OFFSET 1
#define PERI_CFG_ICG_ST_CER_M_LEN    1
#define PERI_CFG_ICG_ST_CER_M_OFFSET 0

#define PERI_CFG_ICG_ST_SFC2X_LEN    1
#define PERI_CFG_ICG_ST_SFC2X_OFFSET 0

#define PERI_CFG_ICG_ST_SFC1X_LEN    1
#define PERI_CFG_ICG_ST_SFC1X_OFFSET 0

#define PERI_CFG_ICG_ST_SDMA_LEN    1
#define PERI_CFG_ICG_ST_SDMA_OFFSET 0

#define PERI_CFG_ICG_ST_TRNG_LEN    1
#define PERI_CFG_ICG_ST_TRNG_OFFSET 0

#define PERI_CFG_ICG_ST_EMMC_LEN    1
#define PERI_CFG_ICG_ST_EMMC_OFFSET 0

#define PERI_CFG_SRST_ST_ITS_LEN    1
#define PERI_CFG_SRST_ST_ITS_OFFSET 0

#define PERI_CFG_SRST_ST_FTE_LEN    1
#define PERI_CFG_SRST_ST_FTE_OFFSET 0

#define PERI_CFG_SRST_ST_DBG_LEN    1
#define PERI_CFG_SRST_ST_DBG_OFFSET 0

#define PERI_CFG_SRST_ST_GPIO_LEN    2
#define PERI_CFG_SRST_ST_GPIO_OFFSET 0

#define PERI_CFG_SRST_ST_WDOG_LEN    11
#define PERI_CFG_SRST_ST_WDOG_OFFSET 0

#define PERI_CFG_SRST_ST_GIC_LEN    1
#define PERI_CFG_SRST_ST_GIC_OFFSET 0

#define PERI_CFG_SRST_ST_UART_LEN    1
#define PERI_CFG_SRST_ST_UART_OFFSET 0

#define PERI_CFG_SRST_ST_MDIO_LEN    2
#define PERI_CFG_SRST_ST_MDIO_OFFSET 0

#define PERI_CFG_SRST_ST_M3_7_LEN       1
#define PERI_CFG_SRST_ST_M3_7_OFFSET    15
#define PERI_CFG_SRST_ST_M3_6_LEN       1
#define PERI_CFG_SRST_ST_M3_6_OFFSET    14
#define PERI_CFG_SRST_ST_M3_5_LEN       1
#define PERI_CFG_SRST_ST_M3_5_OFFSET    13
#define PERI_CFG_SRST_ST_M3_4_LEN       1
#define PERI_CFG_SRST_ST_M3_4_OFFSET    12
#define PERI_CFG_SRST_ST_M3_3_LEN       1
#define PERI_CFG_SRST_ST_M3_3_OFFSET    11
#define PERI_CFG_SRST_ST_M3_2_LEN       1
#define PERI_CFG_SRST_ST_M3_2_OFFSET    10
#define PERI_CFG_SRST_ST_M3_1_LEN       1
#define PERI_CFG_SRST_ST_M3_1_OFFSET    9
#define PERI_CFG_SRST_ST_M3_0_LEN       1
#define PERI_CFG_SRST_ST_M3_0_OFFSET    8
#define PERI_CFG_SRST_ST_M3_POR7_LEN    1
#define PERI_CFG_SRST_ST_M3_POR7_OFFSET 7
#define PERI_CFG_SRST_ST_M3_POR6_LEN    1
#define PERI_CFG_SRST_ST_M3_POR6_OFFSET 6
#define PERI_CFG_SRST_ST_M3_POR5_LEN    1
#define PERI_CFG_SRST_ST_M3_POR5_OFFSET 5
#define PERI_CFG_SRST_ST_M3_POR4_LEN    1
#define PERI_CFG_SRST_ST_M3_POR4_OFFSET 4
#define PERI_CFG_SRST_ST_M3_POR3_LEN    1
#define PERI_CFG_SRST_ST_M3_POR3_OFFSET 3
#define PERI_CFG_SRST_ST_M3_POR2_LEN    1
#define PERI_CFG_SRST_ST_M3_POR2_OFFSET 2
#define PERI_CFG_SRST_ST_M3_POR1_LEN    1
#define PERI_CFG_SRST_ST_M3_POR1_OFFSET 1
#define PERI_CFG_SRST_ST_M3_POR0_LEN    1
#define PERI_CFG_SRST_ST_M3_POR0_OFFSET 0

#define PERI_CFG_SRST_ST_SMB_LEN    1
#define PERI_CFG_SRST_ST_SMB_OFFSET 0

#define PERI_CFG_SRST_ST_CER_S_LEN    1
#define PERI_CFG_SRST_ST_CER_S_OFFSET 1
#define PERI_CFG_SRST_ST_CER_M_LEN    1
#define PERI_CFG_SRST_ST_CER_M_OFFSET 0

#define PERI_CFG_SRSR_ST_TIMER_LEN    30
#define PERI_CFG_SRSR_ST_TIMER_OFFSET 0

#define PERI_CFG_SRST_ST_SFC_BUS_LEN    1
#define PERI_CFG_SRST_ST_SFC_BUS_OFFSET 2
#define PERI_CFG_SRST_ST_SFC2X_LEN      1
#define PERI_CFG_SRST_ST_SFC2X_OFFSET   1
#define PERI_CFG_SRST_ST_SFC1X_LEN      1
#define PERI_CFG_SRST_ST_SFC1X_OFFSET   0

#define PERI_CFG_SRST_ST_SDMA_LEN    1
#define PERI_CFG_SRST_ST_SDMA_OFFSET 0

#define PERI_CFG_SRST_ST_TRNG_LEN    1
#define PERI_CFG_SRST_ST_TRNG_OFFSET 0

#define PERI_CFG_SRST_ST_EMMC_LEN    1
#define PERI_CFG_SRST_ST_EMMC_OFFSET 0

#define PERI_CFG_TSENSOR1_TEMP_READY_LEN    1
#define PERI_CFG_TSENSOR1_TEMP_READY_OFFSET 12
#define PERI_CFG_TSENSOR1_TEMP_OUT_LEN      10
#define PERI_CFG_TSENSOR1_TEMP_OUT_OFFSET   0

#define PERI_CFG_TSENSOR1_VALID_LEN     1
#define PERI_CFG_TSENSOR1_VALID_OFFSET  31
#define PERI_CFG_TSENSOR1_SAMPLE_LEN    10
#define PERI_CFG_TSENSOR1_SAMPLE_OFFSET 0

#define PERI_CFG_MEM_ECC_STATUS_ULTRASOC_LEN    4
#define PERI_CFG_MEM_ECC_STATUS_ULTRASOC_OFFSET 0

#define PERI_CFG_M3_CURRPRI_LEN     8
#define PERI_CFG_M3_CURRPRI_OFFSET  7
#define PERI_CFG_M3_SLEEPING_LEN    1
#define PERI_CFG_M3_SLEEPING_OFFSET 6
#define PERI_CFG_M3_LOCKUP_LEN      1
#define PERI_CFG_M3_LOCKUP_OFFSET   5
#define PERI_CFG_M3_HALTED_LEN      1
#define PERI_CFG_M3_HALTED_OFFSET   4

#define PERI_CFG_PCIE_PERST_STATUS_SOFT_LEN    1
#define PERI_CFG_PCIE_PERST_STATUS_SOFT_OFFSET 0

#define PERI_CFG_EXT_INT_POLARITY_ST_LEN    14
#define PERI_CFG_EXT_INT_POLARITY_ST_OFFSET 0

#define PERI_CFG_EXT_INT_POLARITY_MASK_ST_LEN    14
#define PERI_CFG_EXT_INT_POLARITY_MASK_ST_OFFSET 0

#define PERI_CFG_TRNG_FSM_STATE_LEN      3
#define PERI_CFG_TRNG_FSM_STATE_OFFSET   7
#define PERI_CFG_TRNG_PPROC_STATE_LEN    7
#define PERI_CFG_TRNG_PPROC_STATE_OFFSET 0

#define PERI_CFG_TSENSOR1_ULTRA_OVER_INT_STATUS_LEN    1
#define PERI_CFG_TSENSOR1_ULTRA_OVER_INT_STATUS_OFFSET 2
#define PERI_CFG_TSENSOR1_OVER_INT_STATUS_LEN          1
#define PERI_CFG_TSENSOR1_OVER_INT_STATUS_OFFSET       1
#define PERI_CFG_TSENSOR1_UNDER_INT_STATUS_LEN         1
#define PERI_CFG_TSENSOR1_UNDER_INT_STATUS_OFFSET      0

#define PERI_CFG_PCIE_PERST_INT_STATUS_LEN    1
#define PERI_CFG_PCIE_PERST_INT_STATUS_OFFSET 0

#define PERI_CFG_PWR_CORE_INT_STATUS_LEN    8
#define PERI_CFG_PWR_CORE_INT_STATUS_OFFSET 0

#define PERI_CFG_TSC_SYNC_LEN      1
#define PERI_CFG_TSC_SYNC_OFFSET   12
#define PERI_CFG_BOOT_SEL1_LEN     1
#define PERI_CFG_BOOT_SEL1_OFFSET  11
#define PERI_CFG_BOOT_SEL0_LEN     1
#define PERI_CFG_BOOT_SEL0_OFFSET  10
#define PERI_CFG_IODIE_TYPE_LEN    1
#define PERI_CFG_IODIE_TYPE_OFFSET 9
#define PERI_CFG_TEST_MODE1_LEN    1
#define PERI_CFG_TEST_MODE1_OFFSET 8
#define PERI_CFG_TEST_MODE0_LEN    1
#define PERI_CFG_TEST_MODE0_OFFSET 7
#define PERI_CFG_MPCORE_SEL_LEN    1
#define PERI_CFG_MPCORE_SEL_OFFSET 6
#define PERI_CFG_RST_MODE_LEN      1
#define PERI_CFG_RST_MODE_OFFSET   5
#define PERI_CFG_PROBE_MODE_LEN    1
#define PERI_CFG_PROBE_MODE_OFFSET 4
#define PERI_CFG_DIE_ID_LEN        2
#define PERI_CFG_DIE_ID_OFFSET     2
#define PERI_CFG_SOCKET_ID_LEN     2
#define PERI_CFG_SOCKET_ID_OFFSET  0

#define PERI_CFG_PERI_CFG_VERSION0_LEN    32
#define PERI_CFG_PERI_CFG_VERSION0_OFFSET 0

#define PERI_CFG_PERI_CFG_MAGIC_WORD_LEN    32
#define PERI_CFG_PERI_CFG_MAGIC_WORD_OFFSET 0

#define PERI_CFG_PERI_CFG_ECO_CFG0_LEN    32
#define PERI_CFG_PERI_CFG_ECO_CFG0_OFFSET 0

#define PERI_CFG_PERI_CFG_ECO_CFG1_LEN    32
#define PERI_CFG_PERI_CFG_ECO_CFG1_OFFSET 0

#define PERI_CFG_PERI_CFG_ECO_CFG2_LEN    32
#define PERI_CFG_PERI_CFG_ECO_CFG2_OFFSET 0

#define PERI_CFG_PERI_CFG_ECO_CFG3_LEN    32
#define PERI_CFG_PERI_CFG_ECO_CFG3_OFFSET 0

#define PERI_CFG_SYSCTRL_LOCK_LEN    32
#define PERI_CFG_SYSCTRL_LOCK_OFFSET 0

#define PERI_CFG_SYSCTRL_UNLOCK_LEN    32
#define PERI_CFG_SYSCTRL_UNLOCK_OFFSET 0

#define PERI_CFG_ECO_RSV0_LEN    32
#define PERI_CFG_ECO_RSV0_OFFSET 0

#define PERI_CFG_ECO_RSV1_LEN    32
#define PERI_CFG_ECO_RSV1_OFFSET 0

#define PERI_CFG_ECO_RSV2_LEN    32
#define PERI_CFG_ECO_RSV2_OFFSET 0

#define PERI_CFG_ECO_RSV3_LEN    32
#define PERI_CFG_ECO_RSV3_OFFSET 0

#define PERI_CFG_PROTOTYPE_CLK_LEN    32
#define PERI_CFG_PROTOTYPE_CLK_OFFSET 0

#define PERI_CFG_PROTOTYPE_RST_N_LEN    32
#define PERI_CFG_PROTOTYPE_RST_N_OFFSET 0

#define PERI_CFG_FPGA_VERI_NUM_LEN    32
#define PERI_CFG_FPGA_VERI_NUM_OFFSET 0

#endif // __PERI_CFG_REG_OFFSET_FIELD_H__
